1. Field of the Invention
The invention relates to the field of telecommunication networks, and particularly, to Asynchronous Transfer Mode (ATM) interfaces between different communication layers.
2. Description of Related Art
As telecommunication networks companies design faster communication interfaces, the margin of error in synchronizing signals becomes narrower. Conventional interfaces use a clocking mechanism where receive and transmit clocks are driven from the ATM layer to the physical (PHY) layer. Examples of such interfaces include prior adopted or proposed Universal Test and Operation Physical Layer Protocol Interface for ATM (UTOPIA). Such clocking technique suffices for clock rate operation specified for earlier UTOPIA interfaces.
In a source synchronous interface, a transmit clock signal from a link layer operates as a reference clock for all signals transmitted from the link layer to the PHY layer. A receive clock signal from the PHY layer operates as a reference clock for all the signals transmitted from the PHY layer to the link layer. As a result, receive flow control signals that originate from the link layer are re-synchronized to the transmit clock before transmission to the PHY layer. Similarly, transmit control signals that originate from PHY layer are re-synchronized to the receive clock prior to the transmission to the link layer.
In a proposed UTOPIA Level 4 interface, systems operation is expected to operate at frequencies in excess of 200 MHz, with a bandwidth of over 10 Gbps (giga bit per second). As the frequency of a clock rate increases to above 200 MHz, internal delays on a board caused by secondary delays such as layout and dielectric constants can affect meeting set up time and hold time at endpoints. Consequently, circuit designers are confronted with challenges in resolving asynchronous clock and data signals.
Accordingly, it is desirable to have a method and system for synchronizing clock and data signals from a source clock in ATM interfaces.